A finite impulse response (FIR) filter is a type of electronic filter with a broad range of applications. FIR filters are widely used in both digital signal processing and digital video processing, and their construction is well known in the art.
One type of FIR filter known in the art is a transversal filter, or tapped delay line filter, as shown by circuit 100 in FIG. 1. The output of such a filter 100 is a weighted combination of voltages from impedance elements R1 to R5, which weight samples of an input signal taken from uniformly spaced taps on a delay line, and is thus a weighted sum of the current input value In and a finite number of previous values of the input. Because the outputs of the impedance elements are summed to get the overall output Out, the output is proportional to the sum of the delayed voltages divided by the resistances connected to the respective voltages. The proportionality of the output of the filter of FIG. 1 is thus a constant, the constant being the parallel impedance of all the resistances.
The filter contains a plurality (here 5 are shown) of unit delay elements U1 to U5, each of which introduces a delay of time t. Delay elements U1 to U5 are all clocked by the same clock, so that the input signal propagates at a desired sampling rate. The filter is considered to be of the Mth order, where M−1 is the number of delay elements, so the filter of FIG. 1 is a 6th order filter.
The output of each of the delay elements U1 to U5 is connected at a tap to an element having an impedance value, typically through some buffering means, such as buffers/drivers Z1 to Z5; here, the elements having impedance values are shown as resistors R1 to R5. One of skill in the art will recognize that while this example and the following discussion use resistors to indicate the impedance values for purposes of illustration, other types of circuit elements also have impedance values, for example, capacitors, inductors, or depletion mode MOSFETs, and any device having an impedance that does not otherwise interfere with operation of the filter may be used to provide the desired impedance values as described herein.
The resistors all share a common output point shown as Out on FIG. 1. As an input signal progresses through the delay elements, each resistor causes the signal on the respective delay element to which it is attached to contribute to the output signal in inverse proportion to the resistor value. Thus, if the resistor is small, the signal on the attached delay element will have a larger contribution to the output voltage, while if the resistor is large the contribution to the output will be smaller.
By properly selecting the resistor values in a set of resistors, a FIR filter is designed to provide an output with a desired frequency response. The resistor values are typically calculated by a software program which takes the desired frequency response as an input.
It is well known that the basis of a FIR filter is the mathematics of Fourier transforms. By properly selecting the resistor values in a set of resistors as the inverse of a set of Fourier coefficients that is calculated to provide a desired frequency response, a FIR filter is designed to provide an output with that response. The resistor values are typically calculated by a software program which takes the desired frequency response as an input.
The output of a FIR filter is thus generally characterized by the expression:
  Out  =            ∑              i        =        0            N        ⁢                  In        i            *              W        i            where N is the number of elements in the filter, the values of Wi represent the set of weighting factors implemented by the resistors, and the values of Ini represent a series of delayed versions of the input signal.
In a typical FIR filter, the delay between each value of Ini may be, for example, 1 nanosecond (nS), and the filter may consist of, for example, 30 elements or more. However, this a broad generalization, and there are many variations of both the delay time and the number of elements that are known to those of skill in the art.
The values of Wi and Ini may be continuous, i.e., analog quantities, or may be quantized, i.e., digital or digitally encoded quantities. However, one limitation on an “all analog” FIR filter is the delay elements: although a transmission line is an easy way to implement such delay elements, such a line is impractical to implement on a silicon chip.
One way to avoid this limitation is to use a digital representation of the input signal, i.e., to use values of Ini that are digital which may be easily delayed in a logic circuit; the precise analog signal is not important since all that is necessary to encode a digital signal is whether the signal is high or low relative to some threshold and thus results in a 1 or a 0. A FIR filter built in this way, where the values of the delayed input Ini are digital and the values of the weighting factors Wi are analog, is commonly referred to as a semi-analog FIR filter.
A semi-analog FIR filter is advantageous since it replaces the delay elements that would be needed to delay an analog signal in an analog transmission line with clocked digital delay elements. Such digital delay elements impose two degrees of quantization on the analog signal. First, since the delay elements are clocked, they can only change state on the clock edge, and events are therefore now quantized to the timing edges of the clock. Second, being digital elements, the values of amplitude of their outputs are now just 0 or 1, rather than the original analog qualities. This may be contrasted to an analog transmission line: a delay line constructed from an analog transmission line can pass any signal amplitude and can make a transition between continuous levels at any time.
A semi-analog FIR filter thus has the benefit of a clocked digital delay line, and is thus practical to build on a silicon chip. The delay elements may, for example, be clocked D-flip-flops (DFFs) where the delay time is defined by a common clock, or simply logic gates in which the delay time is the logic gate transition time (known as the “gate delay”). It may be seen that if the input signal to the circuit 100 of FIG. 1 is a digital signal, and the delay elements U1 to U5 are clocked digital delay elements, the circuit is a semi-analog FIR filter, as the output is still the sum of the products from the resistors and thus an essentially continuous analog output.
Using such a semi-analog FIR filter allows any signal that may be conveniently represented in a digital form to be processed by the filter. For example, a square wave signal at 100 megahertz (MHz) may be fed into a delay line consisting of logic gates and the output of the gates summed with the appropriate weighting to make an analog output, and, with the appropriate weightings of Wi, may even generate an analog sine wave from the digital square wave.
In conventional semi-analog FIR filters, current flows continuously through the resistors R1 to R5, and thus power is continuously consumed while the filter is operating. Since such filters are commonly used in signal processing in portable devices, such as smart phones, tablets, and laptop computers, which run on batteries of limited capacity, the power consumption of such filters is part of the total power consumption of the device and contributes to limiting the time the device may be operated before the batteries are drained.